На сайте компании Altera обновлены онлайн-тренинги посвященные OpenCL, Qsys, а также работе с внешней памятью в новых семействах СБИС ПЛ Altera:
- Writing OpenCL Programs for Altera FPGAs
- Running OpenCL on Altera FPGAs
- Introduction to Memory Interfaces IP in Generation 10 Devices
- Integrating Memory Interfaces IP in Generation 10 Devices
- Verifying Memory Interfaces IP in Generation 10 Devices
- On-Chip Debugging of Memory Interfaces IP in Generation 10 Devices
- Introduction to Qsys
- Creating a System Design with Qsys
Кроме того на канале YouTube фирмы Altera размещены новые видеоруководства из серии Engineer to Engineer:
- How to Build the Minimal Preloader (MPL)
- How to Migrate a Quartus II Project to a Different Altera Device
- How to Interoperate ADI AD9680 with Altera JESD204B IP Core on Stratix IV FPGA
- How to Design, Configure, and Execute a Basic Video Streaming Qsys System
- How to Create ADC Design in MAX 10 Devices Using Qsys Tool
- Hard Processor System Implementation with Custom Interconnect in an Altera SoC
- Understanding Avalon-MM Bursting
- How to Order Altera Enpirion Samples
- How to Efficiently Map Shift Register Elements into Altera FPGAs
- Design of Qsys System Showcasing Nios II Processor - SD Card Interface
- SignalTap II Embedded Logic Analyzer Basics
- Voltage Sensor in Arria 10 Devices
- Introduction to JNEye
